1. Field of the Invention
The invention relates to a semiconductor device, in particular, an LDMOS transistor in which a regenerative current or an on-state current of a parasitic bipolar transistor flowing toward the semiconductor substrate is decreased.
2. Description of the Related Art
An LDMOS transistor has higher and more stable switching performance and thus it is easier to use than a bipolar type power transistor, as well as IGBT. Therefore, it is widely used in an inverter circuit of a switching power supply or a lighting device such as a DC-DC converter, an inverter circuit of a motor, and so on. An LDMOS is an abbreviation of Lateral Double Diffused Metal Oxide Semiconductor and means a lateral double-diffused gate MOS.
Among various structures of LDMOS transistors, there is a general LDMOS transistor in which a P type body layer including an N+ type source layer and an N type drift layer including an N+ type drain layer are formed in one of regions in an N type epitaxial layer deposited on a P type semiconductor substrate through an N+ type buried layer, the regions divided by P+ type isolation layers (hereafter, referred to as an ordinary type LDMOS transistor).
A negative voltage, that is generally called a counter-electromotive force, occurring in an inductance load (hereafter, referred to as an L load) such as a motor or the like at the time of a power supply turn-off operation may sometimes be applied to the N+ type drain layer of this LDMOS transistor. At this time, a PN junction formed between the N+ type buried layer and the P type semiconductor substrate becomes forward-biased. Therefore, a so-called regenerative current flows from the N+ drain layer to the P type semiconductor substrate, causing a noise or a faulty operation of the control circuit. A method of preventing such a faulty operation is disclosed in Japanese Patent Application Publication No. 2004-247400 and No. 2005-507164.
When a large negative voltage is applied to the N+ type drain layer, there may also occur a turn-on operation of a parasitic NPN bipolar transistor that uses the N type epitaxial layer as the emitter, the P type semiconductor substrate as the base, and the next N type epitaxial layer etc divided by the P+ type isolation layer as the collector, as well as a regenerative current flow described above.
Furthermore, when the bases and collectors of this parasitic NPN bipolar transistor and an internal parasitic PNP bipolar transistor are connected respectively, both the transistors form a parasitic thyristor. In this case, a leakage current of this parasitic thyristor continues increasing, causing the thermal destruction of the LDMOS transistor at last.
In order to avoid a parasitic thyristor operation problem, an LDMOS transistor as shown in FIG. 3 in which an N+ type drain layer 13, an N type drift layer 8 and an N type epitaxial layer 5 (Hereafter, the three layers will be referred to as a drain region together.) are surrounded by a P type drain isolation layer 6 and this drain region is completely isolated from a P type semiconductor substrate 1 is developed and mass-produced. Hereafter, the description will be continued referring to this LDMOS transistor as a drain isolated type LDMOS transistor.
There exists a parasitic thyristor S in the drain isolated type LDMOS transistor as shown in FIG. 3. However, the on-state operation of this parasitic thyristor S is prevented since an N type layer 5b made of the N type epitaxial layer 5 between the P type drain isolation layer 6 surrounding the drain region and a P type element isolation layer 3 is connected to a ground line through an N+ type guard ring layer 15.
The P type semiconductor substrate 1 as the emitter of the parasitic PNP bipolar transistor that forms the parasitic thyristor S is connected to the ground line, the N+ type buried layer 2 as the base is connected to the ground line through the N type layer 5b and the N+ type guard ring layer 15. Therefore, the parasitic PNP bipolar transistor does not turn on.
However, Japanese Patent Application Publication No. 2004-247400 is directed to only a case where a large negative voltage is applied from a motor load, and does not take account of a case where a large positive voltage is applied to the N+ type drain layer 13. When a large positive voltage is applied to the N+ type drain layer 13 shown in FIG. 3 by some occasion, for example, from an L load at the time of a power supply on/off operation or due to static electricity, capacitive coupling between the N type layer 5a made of the N type epitaxial layer 5 in the drain region and the P type drain isolation layer 6 may cause the P type drain isolation layer 6 to become positive potential.
The P type drain isolation layer 6 may also become positive potential due to hot electrons accelerated by a strong electric field occurring by a large positive voltage inputted to the N+ type drain layer 13. In this case, there occurs the on-state operation of the parasitic PNP bipolar transistor T1 shown in FIG. 3 that uses the P type drain isolation layer 6 as the emitter, the N type layer 5b connected to the ground line as the base, and the P+ type element isolation layer 3 as the collector. As a result, a large current flows from the N+ type drain layer 13 into the P type semiconductor substrate 1, causing problems such as a noise, a faulty operation of the control circuit and so on.
In order to prevent this, as shown in FIG. 2, a high concentration N+ type sinker layer 21 is formed so as to extend from the front surface of the N type epitaxial layer 5 where the N+ type guard ring layer 15 is formed to inside the N+ type buried layer 2. Thus, the base resistance of the parasitic PNP bipolar transistor T2 is decreased, the base-emitter voltage is decreased, and thus the on-state operation of the parasitic PNP bipolar transistor T2 is difficult to occur.
When the N+ type sinker layer 21 is formed, phosphorus (P) or the like is thermally diffused in a high temperature furnace for a long time until it extends into the N+ type buried layer 2. At this time, phosphorus (P) or the like is thermally diffused extending in the lateral direction, too, the N+ type sinker layer 21 occupies most of the width of the surface region of the N type layer 5b, and thus the die size increases.
Therefore, it is necessary to realize a drain isolated type LDMOS transistor that prevents an on-state operation of a parasitic PNP bipolar transistor and prevents an unnecessary surge current flowing from the N+ type drain layer 13 into the P type semiconductor substrate 1 without increase in the die size. Furthermore, it is necessary to realize an ordinary type LDMOS transistor of which the size is the same as that of a drain isolated type LDMOS transistor or smaller and a regenerative current is decreased.